A common design consideration in modern digital systems is the use of clocks of differing clock frequencies in different portions of the system. One example of such a situation arises in microprocessor systems, where the system bus may utilize a clock at a different frequency than the clock utilized by system memory. Data read from memory at one clock frequency may need to be resynchronized to the clock frequency of the system bus. Data written into the memory, conversely, may need to be resynchronized from the clock frequency of the system bus to the clock frequency of the memory. The distinction may be made between source clock domains and destination clock domains. A source clock domain may describe the circuitry that generates a signal in accordance with a source clock, and a destination clock domain may describe the circuitry that receives that signal, but now in accordance with a destination clock. It is noteworthy that this distinction may change many times during the operation of the circuitry. A memory may be within the source clock domain during a data read transaction but may be within the destination clock domain during a data write transaction. Command pulses crossing the boundary from one domain to another may additionally change what is the source clock domain and destination clock domain. More generally, the process of resynchronizing a signal going from a source clock domain into a destination clock domain may be referred to as a clock-crossing scheme.
Simple clock crossing schemes may utilize double synchronous flops in the destination clock domain to cross clock domains. Such methods may add unnecessary latency into the system timing. Therefore such a method may not be particularly attractive when used in higher speed systems, where any delays induced in clock crossing may impact various system latencies. An additional issue may arise with timing of events such as memory reads. If a time period before data signals are valid must be accounted for, when crossing over to the destination clock domain additional delays may be introduced by the clock crossing scheme.